1. Technical Field
Embodiments of the present disclosure relate generally to data error detection technology, and more particularly, to a memory error detection method of a computing device using a baseboard management controller (BMC) of the computing device.
2. Description of Related Art
Memory error often occurs during data transmission of a memory of a computing device. A memory controller may be integrated in a processor of the computing device, such as a network server. When a multiple-bit error of the memory occurs, the processor and a basic input output system (BIOS) of the computing device may stop operating because of an internal error of the processor. Therefore, the multiple-bit error may not be detected by reading state information of a north bridge chip of the computing device through the BIOS, which causes the multiple bit error to not be handled in time.